Analysis for Joint Delay-Power Tradeoff with Buffer/Channel-Aware and Its FPGA Implementation in Wireless Sensor Networks

摘要

In this paper, we aim to investigate the delay-power tradeoff problem which is attracting widespread interest due to its importance in wireless technology. This research has two main objectives. First, to assess the effect of different system parameters on the performance metrics. Second, to provide a solution for this optimization problem. A two-state, slow-fading channel is categorized into good and bad channel states. An adaptive transmission and random data arrivals are considered in our model. Each channel category has its own Markov chain, which is used in modeling the system. A joint Buffer-Aware and Channel-Aware (BACA) problem was introduced. In addition, an enhanced iterative algorithm was introduced for obtaining a sub-optimal delay-power tradeoff. The results show that the tradeoff curve is piecewise linear, convex and decreasing. Furthermore, a channel-aware system was investigated to provide analysis of the effect of system parameters on the delay and power. The obtained results show that the dominant factors that control the system performance are based on the arrival rate and the channel goodness factor. Moreover, a simplified field programable gate array (FPGA) hardware implementation for the channel aware system scheduler is presented. The implementation results show that the consumed power for the proposed scheduler is 98.5 mW and the maximum processing clock speed is 190 MHz.