FPGA Implementation of Ripple Carry and Carry Look Ahead Adders Using Reversible Logic Gates

摘要

Nowadays in the world of VLSI Technology, the word low power consumption is only possible with the concept of Reversible logic design. Reversible concepts will attain more attraction of researchers in the past two decades, mainly due to low-power dissipation and high reliability. It has received great importance due to because of there is no loss of information, while we are processing the data from input to output. Moreover, the power dissipation is also very less and ideally it should be zero. So the concept of reversible design will become more dominant in the low power VLSI design. This paper focuses on the implementation of 4, 8, 16 and 32 bits of highly optimized area efficient Ripple carry adder (RCA) and Carry look ahead (CLA) adders. Finally, we can prove that the Carry look ahead adders are so fastest among all the previously existing designs. All these processes will be Simulated & Synthesized on the ISE Xilinx 14.7 software and it is successfully tested & dumped on the FPGA [2] Spartan-6 kit.