Fast locking technique for phase locked loop based on phase error cancellation

摘要

A fast locking technique for phase locked loop (PLL) is presented. In this technique the resistor of the filter is shorted, while the frequency switching occurs. A time to digital converter (TDC) measures the phase error at the phase frequency detector (PFD) output. The output of the TDC is used to control switches in the voltage control oscillator (VCO) to change the frequency in such a way that minimizes the phase error at the PFD output. Minimizing the phase error at the PFD output will create a zero, which stabilizes the PLL. The bandwidth (BW) is expanded by increasing the charge pump (CP) current. Here, the locking time reduces without stability problem. The simulation of proposed PLL in 180 nm CMOS technology shows a reduction of 75.9 ps locking time from 79 mu s in conventional PLLs to 3.1 mu s. (C) 2019 Elsevier GmbH. All rights reserved.