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Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory

机译:用于3D垂直电阻式随机存取存储器的平面电极厚度缩放的实验研究

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摘要

The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (t_m) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm~2/cell.
机译:研究了多层堆叠3D垂直电阻式随机存取存储器(RRAM)交叉点阵列的垂直缩放比例。用于3D RRAM的多层堆栈的厚度是确定存储密度的关键因素。实验证明了平面电极厚度(t_m)缩小至5 nm的垂直RRAM单元,旨在最小化3D堆叠高度。与先前使用22 nm厚平面电极的演示相比,器件密度可提高5倍。预计对于光刻半节距(F)= 26 nm,一个堆栈的总厚度(T)= 21 nm,可以堆叠37层,从而提供72.8 nm〜2 / cell的位密度。

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