Process design methodology for via-shape-controlled, Cu dual-damascene interconnects tailored in low-k organic film

摘要

Suppression of interconnect RC delay has become very important for 0.1μm-generation CMOS. The key is how to make Cu dual damascene interconnects in low-k film with keeping large misalignment tolerance. This paper describes a new dual hard mask (dHM) process with via-sidewall hardening chemistry for partial via etching to the tow-k organic film without any high-k etch-stop layers. By dual hard mask (dHM) process combined with sidewall-hardening plasma-etching, Cu dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has the low via resistance such as 0.8Ω/0.28μmΦ-via with keeping the large tolerance of misalignment up to 0.1 um-far in via/trench, appreciable for 0.1 μm-generation CMOS ULSIs.