Process integration of low-k organic SOG (k=2.9) for Cu dual-damascene interconnects

摘要

Process integration of low-k organic SOG as interlayer dielectric (ILD) for 0.5 μm-pitch Cu dual-damascene interconnects is discussed. The dual-damascene interconnects using the organic SOG reduced the interconnect capacitance by 30% compared with that using TEOS. The electrical characteristics such as wire and via resistance, showed that the organic SOG ILD are feasible for 0.18μm-CMOS application.