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Integration scheme for cu/low-k interconnects

机译:cu / low-k互连的集成方案

摘要

A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.
机译:提供一种具有在多孔介电层中形成的开口的半导体结构。沿着开口的侧壁的电介质层的暴露的孔被密封。密封可以包括选择性或非选择性沉积方法。密封层在开口的一部分中具有基本均匀的厚度,而在开口的另一部分中具有不均匀的厚度。提供具有孔密封层的镶嵌互连结构及其制造方法。

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