Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM

摘要

This paper proposes a new bitline/plateline precharge and driving scheme for high-speed and high-density chain FeRAM. Both bitline and plateline are precharged to reference level, and cell data is readout by applying bias to ferroelectric capacitor by pulling up plateline and pulling down bitline in access. This scheme suppresses both reliability degradation of cell transistors and signal-loss inherent to chain FeRAM architecture. Furthermore, this scheme reduces the active power dissipation by 10% without access time penalty.