FERROELECTRIC MEMORY ARRAY FOR IMPLEMENTING A ZERO CANCELLATION SCHEME TO REDUCE PLATELINE VOLTAGE IN FERROELECTRIC MEMORY

摘要

Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a negative charge to a memory array bitline through a zero cancellation capacitor while a memory cell plateline signal is applied during a read operation, wherein one or more layers of the zero cancellation system layout is identical or substantially identical to that of the memory cells of the array.