Design of a Field Programmable VLSI Processor Based on Bit-Serial-Pipeline Architectures

摘要

This paper presents a field programmable VLSI processor (FPVLSI) based on bit-serial pipeline architecture that reduces complexity of a programmable interconnection network. The direct allocation of a control/data flow graph (CDFG) is employed where only a single node in a CDFG is mapped into a single cell so that the interconnection complexity is greatly reduced. Two-dimensional mesh network and bit-serial pipeline architecture also reduces the complexity of switch blocks. The FPVLSI with 64 cells is designed in a 0.18μm CMOS design rule. The performance of the FPVLSI is evaluated to be 13 times higher than that of the conventional FPGA in a typical application.