A construction method of path delay faults detectable sequential circuits

摘要

In this paper, we show a construction method of sequential circuits which can detect path delay faults. The proposed method is applied a two-pattern test for path delay faults. Path delay faults have an effect on a value of a register of a sequential circuit. Therefore it is possible to detect path delay faults to observe the value of the register in the sequential circuit: In this paper, we examine the detection condition for path delay faults. We propose a state assignment method which satisfies the detection condition. We show a design example of path delay faults detectable sequential circuits which is adopted the proposed method.