Delay Free Realization of Asynchronous Sequential Switching Circuits Using Constrained Gate Delay Ratios.

摘要

Asynchronous sequential circuits are sequential circuits which do not make use of a synchronizing clock signal. Such asynchronous circuits often fail to perform as predicted by their Boolean descriptions. This is due to the fact that physical switching elements exhibit inertial and stray delays which may cause a network to produce transient outputs unpredictable by Boolean algebra. Circuit malfunctions of this type are referred to as various forms of hazards. Existing methods for elimination of the effects of various types of combinational and sequential hazards may introduce new problems or simply be tedious to use. For example,the effects of combinational hazards can be eliminated by introducing redundant gates. It is the purpose of the paper to demonstrate methods of solving these problems using a knowledge of constrained maximum and minimum gate delays.