Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μmlow power CMOS process

摘要

Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q~2 random walk NMOS current source layout routing method, a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process. The total consumption is only 10 mW from a single 1.2-V power supply, and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively. When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate, the SFDR is measured to be 70 dB. The die area is about 0.2 mm~2.