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首页> 外文期刊>Journal of systems architecture >Register allocation for write activity minimization on non-volatile main memory for embedded systems
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Register allocation for write activity minimization on non-volatile main memory for embedded systems

机译:寄存器分配,用于最小化嵌入式系统非易失性主存储器上的写活动

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Non-volatile memories are good candidates for DRAM replacement as main memory in embedded systems and they have many desirable characteristics. Nevertheless, the disadvantages of non-volatile memory co-exist with its advantages. First, the lifetime of some of the non-volatile memories is limited by the number of erase operations. Second, read and write operations have asymmetric speed or power consumption in non-volatile memory. This paper focuses on the embedded systems using non-volatile memory as main memory. We propose register allocation technique with re-computation to reduce the number of store instructions. When non-volatile memory is applied as the main memory, reducing store instructions will reduce write activities on non-volatile memory. To re-compute the spills effectively during register allocation, a novel potential spill selection strategy is proposed. During this process, live range splitting is utilized to split certain long live ranges such that they are more likely to be assigned into registers. In addition, techniques for re-computation overhead reduction is proposed on systems with multiple functional units. With the proposed approach, the lifetime of non-volatile memory is extended accordingly. The experimental results demonstrate that the proposed technique can efficiently reduce the number of store instructions on systems with non-volatile memory by 33% on average.
机译:非易失性存储器是DRAM替代嵌入式系统中主存储器的良好候选者,它们具有许多理想的特性。然而,非易失性存储器的缺点与它的优点并存。首先,某些非易失性存储器的寿命受到擦除操作次数的限制。其次,读写操作在非易失性存储器中具有不对称的速度或功耗。本文重点介绍使用非易失性存储器作为主存储器的嵌入式系统。我们提出了具有重新计算功能的寄存器分配技术,以减少存储指令的数量。当将非易失性存储器用作主存储器时,减少存储指令将减少非易失性存储器上的写活动。为了有效地重新计算寄存器分配过程中的泄漏,提出了一种新颖的潜在泄漏选择策略。在此过程中,使用有效范围分割来分割某些较长的有效范围,这样它们更有可能被分配到寄存器中。另外,在具有多个功能单元的系统上提出了用于减少重新计算开销的技术。利用所提出的方法,非易失性存储器的寿命相应地延长。实验结果表明,所提出的技术可以有效地将具有非易失性存储器的系统上的存储指令数量平均减少33%。

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