Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

摘要

Due to the demand of high-speed/high-density and low power application of memory devices, tungsten dual poly gate (W-DPG; W/barrier metals+ and p+ poly-Si) electrode could be a good solution in order to reduce gate sheet resistance (R_s). Process optimization is completed for a diffusion barrier metal in a W-DPG. A new noble WSiN layer is inserted between the Ti/WN barrier metal and the tungsten gate electrode to maintain large grain size of W deposited by physical vapor deposition. The annealed WSiN during post-processing changes into crystallized WSi_x mixed with SiN, which can make vertical conductive path between top and bottom interface, contributing to low vertical contact resistance (R_c) and low gate R_s adequate for high speed requirement of memory device. The Ti/WN/WSiN barrier is found to have the same electrical performance, ring oscillator singal delay as complicated multi-layes barrier metal, Ti/WN/TiN/WSi_x/WN reported earlier. Therefore, the gate stack can be optimized by introducing a simpler diffusion barrier metal.