Adaptive Input-Output Selection Based On-Chip Router Architecture

摘要

In this paper, we propose a novel on-chip router architecture, named Adaptive Input-Output Selection (AIOS), for networks-on-chip. The architecture employs efficient input and output selection methods in order to reduce the maximum power consumption and latency of the network. The output selection of AIOS utilizes an adaptive minimal and non-minimal routing algorithm which relies on the congestion condition of neighboring routers to circumvent the congested areas in the network. Moreover, the presented routing scheme is capable of supporting both unicast and multicast communication. When multiple input ports competing for the same output port, the input selection of AIOS serves each input port according to its congestion level to diminish possible network congestion. The simulation results show that in synthetic and realistic traffic profiles the presented router architecture reduces both average latency and maximum power consumption compared to baseline architectures.