Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node

摘要

The minimum operating voltage Vddmin has been measured at low-frequency on chips manufactured in C40 technology node, on a large bitcell and a small, high-density bitcell. Vddmin has been modeled by two methods based on standard Quasi-Monte Carlo (QMC), and by a method named one-Dimensional QMC (1D-QMC), based on the statistical evaluation of the bitcell stability over the full variability space. The QMC@TT and QMC@WC methods are very accurate in predicting Vddmin at 50% or 95% yield levels, respectively, the latter method requiring one fit parameter. The 1D-QMC model agrees within 15 mV with the experimental Vddmin distribution, without the need of any fit parameters.