Analytic modeling of non-uniform graded dopant profile of polysilicon gate in gate tunneling current for N-MOSFET in nanoscale regime

摘要

Aggressive scaling of the gate oxide thickness has made gate tunneling current an essential aspect of the metal-oxide-semiconductor field-effect transistor (MOSFET) modeling. Consequently, the modeling of the different component of gate tunneling current is very important for the estimation of gate leakage power, especially for low power application. In this paper, an analytic model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET including quantization effect and non-uniform dopant profile in vertical direction in poly-gate for sub 50-nm generation MOSFET The results obtained have been compared and contrasted with reported experimental results for the purpose of validation. The agreement found was good, thus validating the developed analytical model. The non-uniform dopant profile in poly-gate has been included in the analytic scheme for the first time. The simplicity of the proposed model is suitable enough to use it for circuit simulator. The proposed model is capable of predicting the gate tunneling current under all bias conditions. It is observed that neglecting the non-uniform dopant distribution in vertical direction in poly gate may lead to large error in the calculated gate tunneling current. The results provide a guideline to the severity of this effect from the point of view of standby power consumption. It is also shown that gate-tunneling current is almost insensitive to temperature. The gate tunneling current variation with gate bias, gate oxide thickness, and source/drain overlap region have also been assessed.