Interface-related Reliability Challenges in 3-D Interconnect Systems with Through-Silicon Vias

摘要

During service, through-silicon vias (TSVs) in vertically stacked-die mi-croelectronic packages are subjected to both thermo-mechanical cycling as well as electromigration. The disparate properties of Cu-filled TSVs and the Si chip induce substantial residual stress-es in both components, as well as at the interface. These stresses may drive serfacial sliding with the interface serving as a rapid diffusion path, re-sulting in significant interfacial strain incompatibilities.