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Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
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1.
Fault injection into SRAM-based FPGAs for the analysis of SEU effects
机译：
故障注入到基于SRAM的FPGA中以分析SEU效应
作者：
Asadi G.
;
Miremadi S.G.
;
Zarandi H.R.
;
Ejlali A.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
SRAM chips;
field programmable gate arrays;
fault tolerance;
fault injection tool;
SRAM based FPGA;
static RAM;
field programmable arrays;
SEU effects;
single event upsets;
industrial applications;
space applications;
reliability;
ion radiation;
configuration bitstream file;
error propagation;
Altera FPGA;
Flex10K200;
benchmark circuits;
2.
Parallel image processing field programmable gate array for real time image processing system
机译：
实时图像处理系统的并行图像处理现场可编程门阵列
作者：
Sugimura T.
;
JeoungChill Shim
;
Kurino H.
;
Koyanagi M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
image processing;
parallel processing;
reconfigurable architectures;
CMOS logic circuits;
multiprocessor interconnection networks;
field programmable gate arrays;
real-time systems;
FPGA;
field programmable gate array;
parallel image processing;
real time image processing system;
configuration memory;
parallel reconfigurable interconnection network;
CMOS technology;
test chip;
chip fabrication;
logic circuits;
0.35 micron;
3.
Using FPGA to implement a n-channel arbitrary waveform generator with various add-on functions
机译：
使用FPGA实现具有各种附加功能的n通道任意波形发生器
作者：
Jen-Wei Hsieh
;
Guo-Ruey Tsai
;
Min-Chuan Lin
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
direct digital synthesis;
function generators;
piecewise linear techniques;
microcomputers;
FPGA/DDS technique;
direct digital synthesis;
field programmable gate arrays;
direct digital synthesizer;
n-channel arbitrary waveform generator;
add-on functions;
prototype design;
PC/FPGA;
AWG;
piecewise linear functions;
PC platform;
USB interface;
n-channel waveform outputs;
control codes;
phase accumulator word length;
personal computers;
frequency resolution;
50 MHz;
0.01164 Hz;
32 bit;
4.
A pattern-matching co-processor for network intrusion detection systems
机译：
用于网络入侵检测系统的模式匹配协处理器
作者：
Clark C.R.
;
Schimmel D.E.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
coprocessors;
safety systems;
field programmable gate arrays;
pattern matching;
finite automata;
logic circuits;
FPGA pattern matching coprocessor;
network intrusion detection systems;
FPGA module;
complex regular expressions;
approximate matching;
bounded substitutions;
bounded insertions;
bounded deletions;
module generator;
nondeterministic finite automata;
standard rule language;
logic complexity;
gigabit line speeds;
5.
Double precision floating-point arithmetic on FPGAs
机译：
FPGA上的双精度浮点算法
作者：
Paschalakis S.
;
Lee P.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
floating point arithmetic;
field programmable gate arrays;
large-scale systems;
floating point arithmetic circuits;
FPGA;
field programmable gate arrays;
complex systems;
general purpose arithmetic unit;
64 bit double precision circuits;
6.
High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications
机译：
适用于基于FPGA和ASIC的应用的高分辨率ADPLL频率合成器
作者：
Stefo R.
;
Schreiter J.
;
Schlussler J.-U.
;
Schuffny R.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
digital phase locked loops;
frequency synthesizers;
field programmable gate arrays;
application specific integrated circuits;
hardware description languages;
oscillators;
jitter;
synchronisation;
frequency dividers;
phase detectors;
ADPLL frequency synthesizer;
all digital PLL;
phase locked loop;
ASIC;
application specific integrated circuits;
ADPLL based clock generator;
digital controlled oscillator;
DCO;
clock signal;
jitter;
VHDL code;
hardware description languages;
semiconductor processes;
design adaptation cost;
V400BG432 VIRTEX FPGA;
field programmable gate arrays;
standard cell libraries;
clock frequency;
lock in time;
reference clock cycles;
40 MHz;
52 MHz;
7.
A high-speed ray tracing engine built on a field-programmable system
机译：
基于现场可编程系统的高速射线追踪引擎
作者：
Fender J.
;
Rose J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
ray tracing;
field programmable gate arrays;
rendering (computer graphics);
prototypes;
high speed ray tracing engine;
field programmable system;
image rendering;
video rendering;
virtual light rays;
3 dimensional scene;
Z buffering methods;
hardware ray tracing system design;
multi FPGA Xilinx Virtex E prototyping system;
field programmable gate array systems;
pentium4 processor;
software ray tracing algorithm;
Virtex 2 Pro FPGA;
AR350 hardware;
2.4 GHz;
8.
A low cost FPGA system for high speed face detection and tracking
机译：
用于高速人脸检测和跟踪的低成本FPGA系统
作者：
Paschalakis S.
;
Bober M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
face recognition;
teleconferencing;
computational complexity;
tracking;
real-time systems;
FPGA face detection;
tracking system;
audiovisual communications;
mobile videoconferencing;
mobile handset;
face stabilisation;
bit rate reduction;
real time applications;
power limited devices;
tracking performance;
computational complexity;
custom hardware;
microprocessors;
memory costs;
high processing rates;
clock speeds;
9.
A parallel look-up logarithmic number system addition/subtraction scheme for FPGA
机译：
FPGA的并行查找对数系统加/减方案
作者：
Lee B.R.
;
Burgess N.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
Chebyshev approximation;
polynomial approximation;
read-only storage;
floating point arithmetic;
parallel look-up logarithmic number system;
addition/subtraction scheme;
FPGA;
critical path;
function approximation;
second order polynomial approximation;
ROM;
logarithmic addition/subtraction function;
better-than-floating-point accuracy;
10.
An architecture for asynchronous FPGAs
机译：
异步FPGA的架构
作者：
Wong C.G.
;
Martin A.J.
;
Thomas P.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
asynchronous circuits;
delay circuits;
logic arrays;
asynchronous FPGA;
asynchronous field programmable gate array;
quasi delay insensitive interconnects;
logic cell;
asynchronous pipeline stage;
timing issues;
place-and-route;
11.
An FPGA implementation of Kak's instantaneously-trained, Fast-Classification neural networks
机译：
Kak即时训练的快速分类神经网络的FPGA实现
作者：
Zhu J.
;
Sutton P.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
neural nets;
backpropagation;
learning (artificial intelligence);
FPGA implementation;
field programmable gate array implementation;
Kak instantaneously trained neural networks;
Kak fast classification neural networks;
biologically plausible short memory sketchpad;
FC network;
training samples;
learning algorithms;
backpropagation;
adaptive filtering;
real time classification;
hardware design;
parameterization;
compile time constant folding;
12.
An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC
机译：
基于FPGA的可重新配置的24位96kHzΣ-Δ音频DAC
作者：
Cheung R.C.C.
;
Pun K.P.
;
Yuen S.C.L.
;
Tsoi K.H.
;
Leong P.H.W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
digital-analogue conversion;
sigma-delta modulation;
pulse code modulation;
embedded FPGA applications;
embedded field programmable applications;
reconfigurable sigma-delta audio DAC;
reconfigurable sigma-delta audio Digital-to-Analog Converter;
SDM design;
sigma-delta modulator design;
input sampling rates;
programmable interpolator;
word lengths;
PCM data;
pulse code modulated data;
CD audio applications;
compact disc audio applications;
SACD audio applications;
DVD audio applications;
digital video disc audio applications;
16 bit;
18 bit;
20 bit;
24 bit;
32 kHz;
44 kHz;
1 kHz;
48 kHz;
88 kHz;
2 kHz;
96 kHz;
13.
An implementation of the Rijndael on Async-WASMII
机译：
Rijndael在Async-WASMII上的实现
作者：
Adachi Y.
;
Ishikawa K.
;
Tsutsumi S.
;
Amano H.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
asynchronous circuits;
data flow graphs;
logic devices;
cryptography;
Rijndael;
Async-WASMII;
data driven virtual hardware system;
multi-context device;
asynchronized operation;
asynchronous reconfigurable device;
PCA;
plast;
14.
Arbitrary function approximation in HDLs with application to the N-body problem
机译：
HDL中的任意函数逼近及其在N体问题中的应用
作者：
Ho C.H.
;
Tsoi K.H.
;
Yeung H.C.
;
Lam Y.M.
;
Lee K.H.
;
Leong P.H.W.
;
Ludewig R.
;
Zipf P.
;
Ortiz A.G.
;
Glesner M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
function approximation;
hardware description languages;
fixed point arithmetic;
N-body problems;
Perl;
function generators;
table lookup;
function approximation;
VHDL modules;
N-body problem;
fixed point precision;
symmetric table addition method;
STAM;
fully-pipelined circuits;
Perl-like language;
function generator module;
hardware description language;
15.
Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture
机译：
在自主可重配置架构上运行的运行时资源管理系统的概念和实现
作者：
Nakane Y.
;
Nagami K.
;
Shiozawa T.
;
Nagoya A.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
information resources;
virtual machines;
high level languages;
run time resource management system;
autonomously reconfigurable architecture;
wired logic computations;
reconfigurable computer;
virtualization;
programmed wired logic;
computing environment;
spatial overheads;
time overheads;
16.
Customising parallelism and caching for machine learning
机译：
自定义并行性和缓存以进行机器学习
作者：
Fidjeland A.
;
Luk W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
parallel architectures;
learning (artificial intelligence);
inductive logic programming;
field programmable gate arrays;
distributed memory systems;
cache storage;
customising parallelism;
machine learning caching;
inductive logic programming;
FPGA based multiprocessor architecture;
field programmable gate array;
coarse grained parallelism;
query level;
fine grained parallelism;
unification algorithm;
hypothesis space;
ground unit clauses;
background knowledge;
distributed memory hierarchy;
organic chemistry data set;
multiple instruction processors;
customised processor;
pentium 4 processor;
Xilinx XCV2000E device;
38 MHz;
1.8 GHz;
17.
Design space exploration with A Stream Compiler
机译：
使用Stream Compiler设计空间探索
作者：
Mencer O.
;
Pearce D.J.
;
Howes L.W.
;
Luk W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
program compilers;
C++ language;
cryptography;
design space exploration;
stream compiler;
hardware accelerators;
hardware design;
software design;
ASC accelerator;
C++ program;
gate level resource;
wavelet compression;
Kasumi encryption;
18.
DIMES: an iterative emulation platform for Multiprocessor-System-On-Chip designs
机译：
DIMES：用于多处理器片上系统设计的迭代仿真平台
作者：
Sakane H.
;
Yakay L.
;
Karna V.
;
Leung C.
;
Gao G.R.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
system-on-chip;
field programmable gate arrays;
modules;
software engineering;
computer architecture;
DIMES;
Delaware iterative multiprocessor emulation system;
iterative emulation platform;
multiprocessor-system-on-chip designs;
multiprocessor SOC design;
FPGA;
field programmable gate arrays;
hardware emulator;
logic systems;
identical functional modules;
cellular architecture;
logic verification;
software development environments;
cost performance;
single module copy;
storage block;
IBM Cyclops architecture;
Cyclops emulation;
19.
Evaluation of network topologies for a run time re-routable network on a programmable chip
机译：
评估可编程芯片上运行时可重新路由网络的网络拓扑
作者：
Kearney D.A.
;
Veldman G.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
network topology;
network routing;
field programmable gate arrays;
IP networks;
token networks;
network topology evaluation;
run time reroutable network;
programmable chip;
IP cores;
field programmable logic domain;
run time reconfiguration;
fixed mesh packet forwarding network topology;
fixed size tiles;
area fragmentation;
variable size cores;
classic network topologies;
FPGA environment;
star connected tristate busses;
token ring arbitration;
RingBuss network;
gate equivalent FPGA;
gate equivalent field programmable gate array;
20.
FPGA implementations of fast fourier transforms for real-time signal and image processing
机译：
快速傅立叶变换的FPGA实现，用于实时信号和图像处理
作者：
Uzun I.S.
;
Bouridane A.A.A.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
fast Fourier transforms;
real-time systems;
signal processing;
image processing;
parallel architectures;
frequency-domain synthesis;
FPGA implementation;
field programmable gate arrays implementation;
1-D FFT;
1-dimensional fast fourier transforms;
real time signal processing;
real time image processing;
computational power;
matrix sizes;
hardware devices;
high level framework;
2-D FFT architecture;
2-dimensional fast fourier transforms architecture;
parallel architecture;
linear speed;
frequency domain image filtering application;
FPGA based parametrisable environment;
21.
FPGA-based computation of free-form deformations in medical image registration
机译：
基于FPGA的医学图像配准中自由形式变形的计算
作者：
Jun Jiang
;
Luk W.
;
Rueckert D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
image registration;
field programmable gate arrays;
medical image processing;
splines (mathematics);
optimisation;
C++ language;
FPGA based designs;
field programmable gate arrays;
medical image registration;
medical image processing;
FFD computation;
free form deformation method;
B-spline algorithm;
three dimensional deformable object modelling;
optimisations;
nested loop;
customer number representation;
third order B-spline model;
conditional statement elimination;
multiple pipelines;
subimage;
Handel-C language;
compile time;
Xilinx XC2V6000 device;
Intel Xeon based PC;
67 MHz;
2666 MHz;
22.
Hierarchical segmentation schemes for function evaluation
机译：
用于功能评估的分层细分方案
作者：
Lee D.-U.
;
Luk W.
;
Villasenor J.
;
Cheung P.Y.K.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
function evaluation;
piecewise polynomial techniques;
table lookup;
rational functions;
hierarchical segmentation scheme;
function evaluation;
piecewise polynomial approximation;
look-up tables;
nonlinear compound functions;
optimum segment boundaries;
finite precision constraints;
high order rational function;
polynomial approximations;
23.
High-level language extensions for run-time reconfigurable systems
机译：
用于运行时可重配置系统的高级语言扩展
作者：
Lee T.K.
;
Derbyshire A.
;
Luk W.
;
Cheung P.Y.K.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
high level languages;
computer networks;
high level language extensions;
run time reconfigurable systems;
reconfigurable hardware blocks;
functional blocks;
dynamic datatypes;
run time parametrisable designs;
Handel C system;
RT pebble tools;
shape adaptive template matching;
shape adaptive network firewall;
24.
Implementation of Elliptic Curve Cryptosystems on a reconfigurable computer
机译：
可重构计算机上椭圆曲线密码系统的实现
作者：
Nguyen N.
;
Gaj K.
;
Caliga D.
;
El-Ghazawi T.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
microprocessor chips;
field programmable gate arrays;
cryptography;
hardware description languages;
elliptic curve cryptosystems;
reconfigurable computer;
microprocessors;
field programmable gate arrays;
FPGA;
computationally intensive problems;
codebreaking;
elliptic curve scalar multiplication;
hardware architecture;
algorithm partitioning strategy;
data transfer;
reconfiguration overheads;
optimized microprocessor;
25.
Improved SVD systolic array and implementation on FPGA
机译：
改进的SVD脉动阵列及其在FPGA上的实现
作者：
Ahmedsaid A.
;
Amira A.
;
Bouridane A.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
singular value decomposition;
field programmable gate arrays;
hardware description languages;
high level languages;
systolic arrays;
SVD systolic array;
singular value decomposition;
FPGA;
field programmable gate arrays;
high level language;
hardware design;
Handel-C language;
BLV array;
Brent-Luk-Van Loan array;
26.
Modular exponentiation using parallel multipliers
机译：
使用并行乘法器的模幂
作者：
Tang S.H.
;
Tsui K.S.
;
Leong P.H.W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
public key cryptography;
embedded systems;
systolic arrays;
modular exponentiation;
parallel multipliers;
field programmable gate array;
FPGA;
RSA public key cryptosystem;
embedded bit multipliers;
carry save addition scheme;
Xilinx XC2V3000-6 device;
RSA decryption;
Chinese remainder theorem;
90 MHz;
0.66 ms;
27.
Networking on chip with platform FPGAs
机译：
使用平台FPGA的片上网络
作者：
Brebner G.
;
Levi D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
system-on-chip;
reconfigurable architectures;
substrates;
wide area networks;
networking on chip;
platform FPGAs;
field programmable gate arrays;
design methodologies;
computer networking;
platform FPGA device;
system on chip substrate;
28.
Performance-driven recursive multi-level clustering
机译：
性能驱动的递归多层集群
作者：
Dehkordi M.E.
;
Brown S.D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
pattern clustering;
delays;
field programmable gate arrays;
graph theory;
recursive multilevel clustering;
delay minimization;
FPGA;
single level clustering algorithm;
netlist transformation;
subcircuit;
node duplication control algorithm;
node slack;
cluster packing algorithm;
Quartus design system;
Altera;
benchmark circuits;
29.
Placement and routing for FPGA architectures supporting wide shallow memories
机译：
支持广泛浅存储器的FPGA架构的布局和布线
作者：
Oldridge S.W.
;
Wilton S.J.E.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
network routing;
integrated memory circuits;
memory architecture;
circuit CAD;
FPGA architectures;
wide shallow memories;
system sized circuits;
FPGA placement;
field programmable gate array architectures;
FPGA routing;
memory resources;
switch block configuration memory;
embedded memories;
routing resources;
routing algorithms;
standard memory architectures;
30.
Product-term based synthesizable embedded programmable logic cores
机译：
基于产品术语的可综合嵌入式可编程逻辑内核
作者：
Yan A.
;
Wilton S.J.E.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
programmable logic devices;
integrated circuit design;
integrated circuit layout;
cellular arrays;
table lookup;
product term based synthesizable embedded programmable logic cores;
post fabrication;
integrated circuit design;
programmable logic fabric;
standard cells;
product term arrays;
lookup table based architectures;
standard benchmark circuits;
integrated circuit layout;
density improvement;
31.
Reconfigurable real-time address trace compressor for embedded microprocessors
机译：
用于嵌入式微处理器的可重新配置的实时地址跟踪压缩器
作者：
Shyh-Ming Huang
;
Ing-Jer Huang
;
Chung-Fu Kao
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
embedded systems;
microprocessor chips;
field programmable gate arrays;
prototypes;
reconfigurable architectures;
program debugging;
reconfigurable RTATC;
reconfigurable real time address trace compressor;
embedded microprocessors;
address data representation;
instruction fetch stage;
address trace information;
FPGA prototyping system;
field programmable gate array prototyping system;
operation workload;
profiling software analysis;
silicon intelligent property;
trace collection;
reconfigurable parameters;
program debugging;
32.
Reconfiguration requirements for high speed wireless communication systems
机译：
高速无线通信系统的重新配置要求
作者：
Pionteck T.
;
Kabulepa L.D.
;
Schlachta C.
;
Glesner M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
telecommunication;
reconfigurable architectures;
field programmable gate arrays;
OFDM modulation;
code division multiple access;
subscriber loops;
radio access networks;
high speed wireless communication systems;
reconfiguration requirements;
hardware platforms;
reconfigurable hardware solutions;
FPGA implementations;
field programmable gate array implementation;
energy penalties;
performance penalties;
application specific hardware designs;
reconfigurable architectures;
OFDM transmission;
orthogonal frequency division multiplexing transmission;
CDMA transmission;
Code Division Multiple Acces transmission;
medium access layers;
market segments;
physical access layers;
33.
Source-directed transformations for hardware compilation
机译：
硬件编译的以源为导向的转换
作者：
Coutinho J.G.F.
;
Luk W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
parallel programming;
C language;
FIR filters;
source-directed transformations;
hardware compilation;
Haydn-C language;
parallel programming;
modular hardware design;
designer productivity;
design quality;
maintainability;
source level transformations;
scheduling;
resource allocation;
FIR filters;
fractal generators;
morphological operators;
morphological erosion design;
34.
TKDM - a reconfigurable co-processor in a PC's memory slot
机译：
TKDM-PC内存插槽中的可重新配置协处理器
作者：
Plessl C.
;
Platzner M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
microcomputers;
field programmable gate arrays;
firmware;
operating systems (computers);
data communication;
TKDM;
reconfigurable co-processor;
PCs memory slot;
reconfigurable computing environment;
FPGA module;
DIMM bus;
dual inline memory module bus;
latency communication;
systems firmware;
Linux;
operating system;
data communication;
FPGA reconfiguration;
data streaming;
programming interfaces;
35.
FPGA implementable architecture for geometric global positioning
机译：
几何全局定位的FPGA可实现架构
作者：
Utgikar A.
;
Seetharaman G.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
Global Positioning System;
field programmable gate arrays;
Hough transforms;
inertial navigation;
computational geometry;
digital arithmetic;
FPGA implementable architecture;
geometric global positioning;
geometric computation;
airborne video camera;
robust Hough transform;
CORDIC structured computation;
coordinate rotation digital computer;
aerial surveillance systems;
GPS;
global positioning system;
inertial navigation sensors;
data correlation;
minimal double precision division;
36.
Seamless top-down flow for quick trial of HW/SW co-design
机译：
无缝的自上而下的流程，可快速试用硬件/软件协同设计
作者：
Nojiri N.
;
Ishii T.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
hardware-software codesign;
field programmable gate arrays;
system-on-chip;
embedded systems;
reconfigurable architectures;
seamless top-down flow;
quick trial;
HW-SW codesign;
hardware-software codesign;
design flow;
embedded system;
system level C description;
field programmable devices;
system level models;
turnaround time;
system level design;
general purpose processor core;
configurable processor core;
37.
A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism
机译：
具有低成本配置数据压缩机制的粗粒度可重新配置体系结构
作者：
Tanigawa K.
;
Kawasaki T.
;
Hironaka T.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
parallel architectures;
data compression;
reconfigurable architecture design;
data compression mechanism;
PARS architecture;
parallel structure architecture;
reconfigurable hardware;
reconfigurable processor;
processor chip design;
FEAL cipher program;
fast data encipherment algorithm;
38.
A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin
机译：
使用空闲跳过循环的动态IP内核的并发多库内存仲裁器
作者：
Kearney D.A.
;
Veldman G.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
SRAM chips;
field programmable gate arrays;
computer interfaces;
instruction sets;
multibank memory arbiter;
dynamic IP cores;
idle skip round robin;
multiple internal networks;
programmable chip;
SRAM chips;
instruction set;
atomic test;
FPGA;
field programmable gate arrays;
39.
A crystal-based digital ring oscillator
机译：
基于晶体的数字环形振荡器
作者：
Abdollahi S.R.
;
Fakhraei S.M.
;
Bakkaloglu B.
;
Kamarei M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
voltage-controlled oscillators;
digital phase locked loops;
transceivers;
phase noise;
crystal based digital ring oscillator;
multichannel digitally controlled oscillator design;
MDCO design;
complementary metal oxide semiconductor;
CMOS process;
Altera FPGA;
field programmable gate array;
digital wireless transceivers;
digital cable transceivers;
crystal based delay cells control;
propagation delay;
reduced phase noise;
analog based DCOs;
0.16 mW;
2.3 V;
40.
A field-customizable and runtime-adaptable microarchitecture
机译：
可现场定制和运行时自适应的微体系结构
作者：
Sato T.
;
Morishita D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
systems analysis;
reconfigurable architectures;
microcomputers;
field customizable microarchitecture;
runtime adaptable microarchitecture;
hardware/software adaptable microprocessors;
microprocessor hardware;
41.
A new approach for reconfigurable massively parallel computers
机译：
可重构大规模并行计算机的新方法
作者：
Bodba C.
;
Danne K.
;
Ahmadinia A.
;
Teich J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
reconfigurable architectures;
network topology;
trees (mathematics);
parallel processing;
reconfigurable parallel computers;
FPGA;
field programmable gate arrays;
tree topology;
parallel computation;
reconfigurable topology;
physical topology;
virtual ring topology;
42.
A parameterized automatic cache generator for FPGAs
机译：
用于FPGA的参数化自动缓存生成器
作者：
Yiannacouras P.
;
Rose J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
cache storage;
memory architecture;
field programmable gate arrays;
parameterized automatic cache generator;
FPGA;
field programmable gate array;
storage components;
43.
A temporal partitioning approach based on reconfiguration granularity estimation for dynamically reconfigurable systems
机译：
基于可重构粒度估计的动态可重构系统的时间划分方法
作者：
Xue-Jie Zhang
;
Kam-Wing Ng
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
high level synthesis;
logic partitioning;
reconfigurable architectures;
C++ language;
temporal partitioning techniques;
reconfiguration granularity estimation;
dynamically reconfigurable systems;
high level synthesis;
HLS;
cost models;
fixed reconfigurable resource constraints;
DRS design space exploration;
reconfiguration overhead;
temporal partitioning problems;
interconnected operations;
communication cost evaluation;
44.
An FPGA implementation of a special purpose processor for steganography
机译：
用于隐写术的专用处理器的FPGA实现
作者：
Farouk H.A.
;
Saeb M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
microprocessor chips;
cryptography;
data encapsulation;
field programmable gate arrays;
special purpose processor;
FPGA implementation;
steganography;
prisoners' problem;
field programmable gate arrays;
audio steganographic model;
video steganographic model;
secret key steganographic microarchitecture;
subliminal communication channel;
45.
Beyond performance: secure and fair memory management for multiple systems on a chip
机译：
超越性能：对片上多个系统的安全且公平的内存管理
作者：
Macian C.
;
Dharmapurikar S.
;
Lockwood J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
storage management chips;
system-on-chip;
quality of service;
VLSI;
DRAM chips;
memory management;
multiple systems on a chip;
MSoC;
VLSI technologies;
very large scale integration;
off chip resources;
QoS guarantees;
quality of service;
embedded hardware manager;
resource manager;
security agent;
resource misuse;
46.
Exploiting system-level parallelism in the application development on a reconfigurable computer
机译：
在可重配置计算机上的应用程序开发中利用系统级并行性
作者：
El-Araby E.
;
Taher M.
;
Gaj K.
;
El-Ghazawi T.
;
Caliga D.
;
Alexandridis N.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
computation theory;
microprocessor chips;
microcomputers;
system level parallelism;
reconfigurable computer;
FPGA;
field programmable gate arrays;
hardware functionality;
I/O time;
computation time;
DMA transfer;
microprocessor memory;
onboard memory;
state of the art reconfigurable platform;
reconfigurable machine;
47.
A reconfigurable future
机译：
可重构的未来
作者：
Bishop P.
;
Sullivan C.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
field programmable gate arrays;
digital signal processing chips;
software tools;
system-on-chip;
hardware-software codesign;
reconfigurable architectures;
programmable structures;
architectural components;
DSP blocks;
digita;
48.
An autonomous flying object navigated by real-time optical flow and visual target detection
机译：
通过实时光流和视觉目标检测导航的自主飞行物体
作者：
Yamada H.
;
Tominaga T.
;
Ichikawa M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
image sequences;
navigation;
CMOS image sensors;
video cameras;
field programmable gate arrays;
attitude control;
aerospace control;
machine control;
autonomous flying object navigation;
real time optical flow;
visual target detection;
CMOS video cameras;
complementary metal oxide semiconductor;
FPGA;
field programmable gate arrays;
indoor autonomous flying object;
recursive integration;
masking optical flow;
signal to noise ratio;
flying objects attitude;
target detection process;
visual processing;
nonlinear controlling processes;
Xilinx XC2V1500;
49.
FPGA based EBCOT architecture for JPEG 2000
机译：
JPEG 2000的基于FPGA的EBCOT架构
作者：
Gangadhar M.
;
Bhatia D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
image coding;
field programmable gate arrays;
hardware description languages;
parallel architectures;
FPGA based EBCOT architecture;
field programmable gate arrays;
JPEG 2000;
joint photographic experts group;
embedded block coding with optimized truncat;
50.
FPGA-based high-speed emulator of quantum computing
机译：
基于FPGA的量子计算高速仿真器
作者：
Fujishima M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
quantum computing;
field programmable gate arrays;
optimisation;
Fourier transforms;
FPGA based high speed emulator;
field programmable gate array;
quantum computing;
quantum computers;
NP problems;
nondeterministic polynomial problems;
periodic function;
quantum bits;
quantum algorithm;
hardware emulator;
51.
Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform FPGAs
机译：
抽象和原语支持使用虚拟平台FPGA为动态IP内核分配运行时资源
作者：
Kearney D.A.
;
Veldman G.
;
Warren D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
resource allocation;
VLSI;
online operation;
runtime resource allocation;
dynamic IP cores;
virtual platform FPGA;
hardware design;
VLSI chip;
platform design;
run time reconfiguration;
application programmers interface;
52.
Accelerating signal processing algorithms in digital holography using an FPGA platform
机译：
使用FPGA平台加速数字全息术中的信号处理算法
作者：
Lenart T.
;
Owall V.
;
Gustafsson M.
;
Sebesta M.
;
Egelberg P.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
holography;
image reconstruction;
hardware description languages;
image sensors;
real-time systems;
accelerate image processing algorithms;
DSP system;
digital signal processing;
digital holography;
FPGA platform;
real-time image reconstruction;
HDL simulation;
hardware description language;
image sensor;
field programmable gate arrays;
external components;
53.
An FPGA based coprocessor for 3D affine transformations
机译：
基于FPGA的3D仿射变换协处理器
作者：
Bensaali F.
;
Amira A.
;
Bouridane A.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
coprocessors;
field programmable gate arrays;
computer graphics;
CAD;
data visualisation;
matrix multiplication;
high level languages;
microcomputers;
FPGA hardware;
coprocessor;
3D affine transformations;
field programmable gate array;
3D graphics accelerators;
computing application;
PC systems;
personal computer system;
computer aided design;
CAD;
visualization;
matrix multiplication;
3D models;
RC1000-PP Celoxica board;
Handel-C language;
flexible data size;
54.
Architecture template with dynamic buffering for runtime reconfiguration of adaptive embedded communication systems
机译：
具有动态缓冲的体系结构模板，用于自适应嵌入式通信系统的运行时重新配置
作者：
Eilers D.
;
Steckenbiller H.
;
Knorr R.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
embedded systems;
reconfigurable architectures;
distributed processing;
adaptive signal processing;
adaptive systems;
field programmable gate arrays;
architecture template;
adaptive embedded communication systems;
distributed dynamic buffering;
runtime reconfiguration;
adaptive processing architectures;
FPL;
field programmable logic;
adaptive signal processing;
real-time constraints;
55.
Artificial neural networks as building blocks of mixed signal FPGA
机译：
人工神经网络作为混合信号FPGA的基础
作者：
Manjunath R.
;
Gurumurthy K.S.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
mixed analogue-digital integrated circuits;
field programmable gate arrays;
field programmable analogue arrays;
neural nets;
learning (artificial intelligence);
feedback;
ANN;
artificial neural networks;
mixed signal FPGA;
field programmable gate arrays;
FPAA;
field programmable analogue arrays;
CAB;
configurable analog blocks;
differential feedback technique;
arbitrary system;
Si;
56.
Augmenting general purpose processors for network processing
机译：
增强通用处理器以进行网络处理
作者：
Ghasemi H.R.
;
Mohammadi H.
;
Robatmili B.
;
Yazdani N.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
instruction sets;
reduced instruction set computing;
network routing;
protocols;
general purpose processors;
network processing;
packet processing;
network processor design;
network protocols;
ASIC;
application specific integrated circuit;
GPP;
general purpose processor;
instruction sets;
57.
Bayesian digital terrain model reconstruction on Virtex-II FPGA
机译：
在Virtex-II FPGA上重建贝叶斯数字地形模型
作者：
Han Tao
;
Khoong T.L.
;
Serena C.G.L.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
topography (Earth);
photogrammetry;
image reconstruction;
geophysics computing;
Bayesian digital terrain model reconstruction;
Bayesian DTM reconstruction algorithm;
Virtex-II FPGA;
field programmable gate arrays;
3D discr;
58.
Combined run-time area allocation and long line re-routing for reconfigurable computing
机译：
结合了运行时区域分配和长线重新路由，可重新配置计算
作者：
Jasiunas M.D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
statistical distributions;
network routing;
prototypes;
online operation;
operating systems (computers);
resource allocation;
run time area allocation;
long line rerouting;
reconfigurable computing;
online algorithms;
rout;
59.
Comparing the bitstreams of applications specified in Hardware Join Java and HandelC
机译：
比较在Hardware Join Java和HandelC中指定的应用程序的位流
作者：
Hopf J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
Java;
C language;
hardware description languages;
hardware join Java;
FPGA bitstreams;
HandelC;
Xilinx foundation tools;
multiplication operation synthesis;
addition operation synthesis;
60.
Compiling to FPGAs via an EPIC compiler's intermediate representation
机译：
通过EPIC编译器的中间表示形式编译为FPGA
作者：
Zhiguo Ge
;
Jirong Liao
;
Weng-Fai Wong
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
optimising compilers;
reconfigurable architectures;
field programmable gate arrays;
flow graphs;
FPGA hardware;
field programmable gate arrays;
EPIC compiler;
explicitly parallel instruction computing;
reconfigurable systems;
hardware resource;
system level description;
software intermediate representation;
state of the art optimizing compiler;
C programs;
EPIC processor;
control flow graph;
register transfer level;
RTL level verilog description;
reconfigurable HW device;
translation process;
61.
Design of FPGA-based adaptive remote calibration control system
机译：
基于FPGA的自适应远程校准控制系统设计
作者：
Yuan-Long Jeang
;
Liang-Bi Chen
;
Chia-Pin Huang
;
Yu-Hsiang Hsu
;
Ming-Yu Yeh
;
Kai-Ming Yang
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
adaptive control;
telecontrol;
calibration;
servomotors;
control system synthesis;
feedback;
Internet;
local area networks;
FPGA;
field programmable gate arrays;
adaptive remote calibration control system design;
servomotors;
robot control;
factory automation;
real time response;
system control feedbacks;
calibration control feedbacks system;
remote monitoring;
proportional integration derivative parameters;
PID;
Internet;
LAN;
local area networks;
62.
Design of low cost FPGA based PCI Bus Sniffer
机译：
基于低成本FPGA的PCI总线嗅探器的设计
作者：
Chee Wei Liang
;
Zain Ali N.B.
;
Seth Nair R.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
hardware description languages;
field programmable gate arrays;
system buses;
FPGA design;
field programmable gate array;
PCI bus sniffer;
peripheral component interconnect bus sniffer;
PCI bus analyzer;
PCI signals;
semiconductor industries;
freeware tools;
hardware design;
Verilog hardware development language;
HDL;
SPARTAN II;
Xilinx;
63.
FPGA implementation of real-time image convolutions with three level of memory hierarchy
机译：
具有三级存储器层次结构的实时图像卷积的FPGA实现
作者：
Hongtu Jiang
;
Owall V.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
memory architecture;
image processing;
control system synthesis;
finite state machines;
FPGA implementation;
field programmable gate arrays;
real time image convolutions;
memory hierarchy exploration;
image convolution processor;
Xilinx VirtexE FPGA;
pipelined datapath;
streamlined data flow;
C64x processor;
clock frequency;
I/O bandwidth reduction;
potential power savings;
ASIC implementation;
application specific integrated circuits;
finite state machine;
incremental branch optimization;
data transfer;
control system synthesis;
64.
Mapping computation kernels to clustered programmable-reconfigurable processors
机译：
将计算内核映射到群集的可编程可重新配置处理器
作者：
Cook J.J.
;
Baugh L.W.
;
Gottlieb D.B.
;
Carter N.P.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
finite state machines;
program compilers;
data flow graphs;
mapping computation Kernel;
clustered programmable reconfigurable processor;
reconfigurable computing systems;
processor architecture;
compilation time;
Amalgam reconfigurable clusters;
gated singular assignment program;
parallel intermediate program representation;
FSM;
finite state machines;
datapath synthesis tool;
65.
Multisensor inversion with high-performance FPGA computation
机译：
高性能FPGA计算的多传感器反演
作者：
Yongxiang Hu
;
Yang Cai
;
Tomzak M.
;
Lee T.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
geophysics computing;
field programmable gate arrays;
inverse problems;
sensor fusion;
radiative transfer;
multisensor inversion;
FPGA computation;
reconfigurable generalized inversion processor;
generalized nonlinear regression algorithm;
radiative transfer simulation;
autonomous detection;
satellite measurement signatures;
multiplatform sensors;
redundant algorithm development;
autonomous onboard image analysis;
physics based data compressions;
66.
On-chip communication architectures for reconfigurable System-on-Chip
机译：
用于可重配置片上系统的片上通信体系结构
作者：
Lee A.S.
;
Bergmann N.W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
systems analysis;
system-on-chip;
reconfigurable architectures;
system buses;
onchip communication architectures;
reconfigurable system on chip;
RSOC design;
system on chip designs;
serial bus;
packet switched network;
67.
Performance optimization of an FPGA-based configurable multiprocessor for matrix operations
机译：
基于FPGA的可配置多处理器用于矩阵运算的性能优化
作者：
Xiaofang Wang
;
Ziavras S.G.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
sparse matrices;
parallel processing;
hardware-software codesign;
shared memory systems;
computational complexity;
performance optimization;
FPGA chip;
field programmable gate array chip;
configurable multiprocessor;
matrix operations;
configurable computing;
parallel processing;
hardware-software codesign;
shared memory implementation;
parallel LU factorization;
sparse block diagonal bordered matrices;
BDB;
multiprocessor design;
68.
Reconfigurable parallel comparation architecture and its application to IP packet filters
机译：
可重配置的并行比较架构及其在IP数据包过滤器中的应用
作者：
Aibe N.
;
Yasunaga M.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
programmable filters;
reconfigurable architectures;
field programmable gate arrays;
parallel architectures;
comparators (circuits);
prototypes;
RPCA;
reconfigurable parallel comparation architecture;
IP packet filters;
FPGA;
variable comparator;
RealTeK RTL8201BL chip;
packet filter prototype;
XILINX XCV300E-6PQ240C chip;
speed/data-size tradeoff;
69.
Specification and integration of software and reconfigurable hardware using Hardware Join Java
机译：
使用Hardware Join Java规范和集成软件和可重新配置硬件
作者：
Hopf J.
;
Kearney D.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
very high speed integrated circuits;
hardware description languages;
high level languages;
Java;
integrated software;
reconfigurable architectures;
benchmark testing;
program compilers;
software integration;
reconfigurable hardware;
mixed hardware/software reconfigurable systems;
high level specification language;
hardware join Java;
FPGA;
field programmable gate arrays;
software hardware interface;
RTL VHDL;
resistor-transistor logic;
very high speed integrated circuits;
hardware description language;
benchmarking;
compilers;
70.
Temporal task clustering for online placement on reconfigurable hardware
机译：
时间任务集群，可在线放置在可重新配置的硬件上
作者：
Ahmadinia A.
;
Bobda C.
;
Teich J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
multiprogramming;
workstation clusters;
field programmable gate arrays;
cost reduction;
temporal task clustering;
online cluster placement;
reconfigurable hardware;
FPGA;
field programmable gate arrays;
multitasking systems;
communication cost reduction;
inter-task communication;
71.
The Egret platform for reconfigurable system on chip
机译：
用于可重配置片上系统的Egret平台
作者：
Bergmann N.W.
;
Williams J.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
system-on-chip;
embedded systems;
systems analysis;
operating systems (computers);
system buses;
Egret platform;
reconfigurable system on chip technology;
embedded systems;
RSOC design;
operating system;
processor;
backplane buses;
RSOC prototyping platform;
72.
The Multiplier Tree FIR filter architecture
机译：
乘数树FIR滤波器架构
作者：
Carreira A.
;
Fox T.W.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
FIR filters;
trees (mathematics);
computer architecture;
multiplier tree FIR filter architecture;
redundant arithmetic elements;
constant coefficient multipliers;
hardware cost filter;
hardware cost;
73.
Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization
机译：
使用基于FPGA的金字塔实现的三个视频应用程序：跟踪，马赛克和稳定化
作者：
Nuno-Maganda M.A.
;
Arias-Estrada M.O.
;
Feregrino-Uribe C.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
image segmentation;
target tracking;
image resolution;
image representation;
field programmable gate arrays;
C language;
video applications;
FPGA based pyramid;
hardware modules;
target tracking;
image stabilization;
image mosaicking;
pyramidal module;
multiresolution correlation module;
C language;
Celoxica RC1000 development platform;
Virtex-E FPGA;
74.
An embedded in-circuit emulator generator for SOC platform
机译：
用于SOC平台的嵌入式在线仿真器生成器
作者：
Yuan-Long Jeang
;
Liang-Bi Chen
;
Yi-Ting Chou
;
Hsin-Chia Su
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
system-on-chip;
user interfaces;
microcontrollers;
hardware description languages;
IEEE standards;
terminal emulation;
embedded incircuit emulator generator;
EICE generator;
SOC platform;
system on chip;
embedded ICE design;
macrocontrollers;
chip testin;
75.
An FPGA based coprocessor for large matrix product implementation
机译：
基于FPGA的协处理器，用于大矩阵产品实现
作者：
Bensaali F.
;
Amira A.
;
Bouridane A.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
field programmable gate arrays;
coprocessors;
matrix multiplication;
programming languages;
hardware description languages;
FPGA;
coprocessor;
matrix product algorithm;
matrix multiplication;
image processing;
signal processing;
Handel-C;
VHDL;
programming languages;
partitioning;
RC1000-PP Celoxica board;
76.
Reconfigurable architecture for probabilistic neural network system
机译：
概率神经网络系统的可重构架构
作者：
Mizuno R.
;
Aibe N.
;
Yasunaga M.
;
Yoshihara I.
会议名称：
《Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on》
|
2003年
关键词：
reconfigurable architectures;
probabilistic logic;
neural nets;
field programmable gate arrays;
image recognition;
program processors;
reconfigurable architecture;
PNN;
probabilistic neural network;
PNN hardware system;
FPGA;
field programmable gate arrays;
preprocessing circuits;
image recognition;
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