High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications

摘要

A hardware implementation of an ADPLL-based clock generator is presented. The digital controlled oscillator (DCO) used in the ADPLL generates a clock signal with a high frequency resolution and a small jitter. The presented ADPLL has a fast acquisition and a large pull-in range. The whole design including the DCO has been described in synthesizable VHDL. It does not contain library specific cells, and can be synthesized independently of the standard cell library. Thus, it is portable and the time required to fit it for different semiconductor processes is reduced considerably. The design adaptation cost is limited to adjustment of a few constants in the VHDL-code. The presented design has been implemented in a V400BG432 VIRTEX FPGA and it has been synthesized using two different standard cell libraries (CMOS AMS 0.6 /spl mu/m and CMOS AMS 0.35 /spl mu/m). The maximum achievable clock frequency is 40 MHz using the FPGA and 52 MHz using the above mentioned standard cell libraries. The maximal lock-in time of the ADPLL is 30 reference clock cycles.