首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors
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Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

机译:超高功率处理器中长期工作量依赖性BTI降解产生的功能误差分析

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Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, bias temperature instability (BTI) is a degradation effect that changes the threshold voltage of transistors. Its effect is more prevalent as the scaling of transistor dimensions progresses. In this work, we present a method to enable defect-centric long-term modeling of BTI degradation that takes into account the effects of concrete workloads at the processor data path level. Based on this study, we propose a novel design flow to link the impact of BTI degradation at the transistor (Delta Vth), processor data path (e.g., maximum frequency) and application-functionality levels. This flow may be used to improve system correctness over the entire device lifetime, avoiding unsafe working points, or to achieve a graceful degradation of system characteristics. Our design flow is applicable to all types of digital circuits, including high-performance processors. However, in this specific work we focus on the domain of biosignal processing applications for wireless body sensor networks (WBSNs), the pseudoperiodic nature of which interacts with the partially recoverable nature of BTI. Our results in this domain show, for a 32-nm implementation, a variation of up to 54.6 mV in the threshold voltage of the circuit transistors after one year of continuous operation, with an impact of 8.4% in the maximum safe operating frequency. Such effects are expected to strongly worsen for longer lifetimes and more scaled technology nodes.
机译:数字电路中的老化效果改变其晶体管的切换特性,从而导致时间违规,这可能导致系统级功能误差。特别地,偏置温度不稳定性(BTI)是改变晶体管的阈值电压的劣化效果。随着晶体管尺寸的缩放进行,其效果更为普遍。在这项工作中,我们提出了一种方法来实现BTI劣化的缺陷的长期建模,以考虑混凝土工作负载在处理器数据路径级别的影响。基于这项研究,我们提出了一种新颖的设计流程,将BTI劣化的影响联系在晶体管(Delta Vth),处理器数据路径(例如,最大频率)和应用程序功能级别中的影响。该流程可用于改善整个设备寿命的系统正确性,避免不安全的工作点,或者实现系统特征的优雅降低。我们的设计流程适用于所有类型的数字电路,包括高性能处理器。然而,在该具体工作中,我们专注于无线体传感器网络(WBSNS)的生物信号处理应用领域,其伪状性质与BTI的可部分可回收性质相互作用。我们的结果在该域显示,对于32nm实现,在连续运行一年后电路晶体管阈值电压的变化在电路晶体管的阈值电压中变化,最大安全工作频率的影响为8.4%。预计这种效果将强烈恶化,以便更长的生命和更缩放的技术节点。

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