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A 2-D Calibration Scheme for Resistive Nonvolatile Memories

机译:电阻非易失性存储器的2-D校准方案

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Resistive nonvolatile memories (NVMs) promise significant performance improvement over existing NVM candidates. However, fabrication nonidealities and parasitics on the access path cause cell location-dependent variations in the total resistance received at the read circuitry. Write characteristics delivered to each cell, as well as the optimal write conditions for each cell, are also location-dependent. In this article, we propose a 2-D calibration scheme to address these variations. The proposed scheme joins row and column calibrations to create a correction grid at each crosspoint on the array and effectively cancels many spatial patterns. The enabling circuit and algorithmic modifications are described. We assess the 2-D calibration scheme in a 28-nm $256imes 256$ memory array, and show reduction in variability across multiple gradient patterns compared to conventional calibration methods. For the same calibration granularity, 2-D calibration achieves between 41% and 99% improvement depending on the amount of calibration bits. For the same amount of total calibration bits, the 2-D calibration scheme reduces the variability between 39% and 99%.
机译:电阻非易失性存储器(NVMS)承诺对现有的NVM候选人的显着性能改善。然而,在接入路径上的制造非侵入性和寄生剂导致在读取电路上接收的总电阻的单元定位依赖性变化。将传送到每个单元的写特性以及每个单元的最佳写条件也是依赖的。在本文中,我们提出了一个2-D校准方案来解决这些变化。所提出的方案加入行和列校准,以在阵列上的每个交叉点处创建校正网格,并有效地取消许多空间模式。描述了启用电路和算法修改。与传统校准方法相比,我们评估了28纳米256美元的256美元倍的256美元次的256 $内存阵列的校准方案,并显示多种梯度模式的可变性降低。对于相同的校准粒度,根据校准位的量,2-D校准达到41%和99%的改善。对于相同量的总校准比特,2-D校准方案可降低39%和99%之间的可变性。

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