Ravel-XL: a hardware accelerator for assigned-delay compiled-codelogic gate simulation

摘要

Ravel-XL is a single-board hardware accelerator for gate-levelndigital logic simulation. It uses a standard levelized-code approach tonstatically schedule gate evaluations. However, unlike previousnapproaches based on levelized-code scheduling, it is not limited tonzero- or unit-delay gate models and can provide timing accuracyncomparable to that obtained from event-driven methods. We review thensynchronous waveform algebra that forms the basis of the Ravel-XLnsimulation algorithm, present an architecture for its hardwarenrealization, and describe an implementation of this architecture as ansingle VLSI chip. The chip has about 900000 transistors on a die that isnapproximately 1.4 cm2, requires a 256 pin package and isndesigned to run at 33 MHz. A Ravel-XL board consisting of the processornchip and local instruction and data memory can simulate up to onenbillion gates at a rate of approximately 6.6 million gate evaluationsnper second. To better appreciate the tradeoffs made in designingnRavel-XL, we compare its capabilities to those of other commercial andnresearch software simulators and hardware accelerators