The impact of intra-die device parameter variations on path delaysand on the design for yield of low voltage digital circuits

摘要

The yield of low voltage digital circuits is found to he sensitivento local gate delay variations due to uncorrelated intra-die parameterndeviations. Caused by statistical deviations of the doping concentrationnthey lead to more pronounced delay variations for minimum transistornsizes. Their influence on path delays in digital circuits is verifiednusing a carry select adder test circuit fabricated in 0.5 and 0.35 Μmncomplementary metal-oxide-semiconductor (CMOS) technologies with twondifferent threshold voltages. The increase of the path delay variationsnfor smaller device dimensions and reduced supply voltages as well as thendependence on the path length is shown. It is found that circuits with anlarge number of critical paths and with a low logic depth are mostnsensitive to uncorrelated gate delay variations. Scenarios for futurentechnologies show the increased impact of uncorrelated delay variationsnon digital design. A reduction of the maximal clock frequency of 10% isnfound for, for example, highly pipelined systems realized in an0.18-Μm CMOS technology