Exploring the design space of mixed swing quadrail for low-powerdigital circuits

摘要

This paper describes and explores the design space of a mixednvoltage swing methodology for lowering the energy per switchingnoperation of digital circuits in standard submicron complementarynmetal-oxide-semiconductor (CMOS) fabrication processes. Employing mixednvoltage swings expands the degrees of freedom available in thenpower-delay optimization space of static CMOS circuits. In order tonstudy this design space and evaluate the power-delay tradeoffs,nanalytical polynomial formulations for power and delay of mixed swingncircuits are derived and HSPICE simulation results are presented tondemonstrate their accuracy. Efficient voltage scaling and transistornsizing techniques based on our analytical formulations are proposed fornoptimizing energy/operation subject to target delay constraints; up ton2.2× improvement in energy/operation is demonstrated for annISCAS'85 benchmark circuit using these techniques. Experimental resultsnfrom HSPICE simulations and measurements from an And-Or-Invert (AO1222)ntest chip fabricated in the Hewlett-Packard 0.5 Μm process arenpresented to demonstrate up to 2,92× energy/operation savings fornoptimized mixed swing circuits compared to static CMOS