The use of nanoelectronic devices in highly parallel computingsystems

摘要

The continuing development of smaller electronic devices into thennanoelectronic regime offers great possibilities for the construction ofnhighly parallel computers. This paper describes work designed tondiscover the best ways to take advantage of this opportunity. Simulatednresults are presented which indicate that improvements in clock rates ofntwo orders of magnitude, and in packing density of three orders ofnmagnitude, over the best current systems, should be attainable. Thesenresults apply to the class of data-parallel computers, and theirnattainment demands modifications to the design which are also described.nEvaluation of the requirements of alternative classes of parallelnarchitecture is currently under way, together with a study of thenvitally important area of fault-tolerance