Statistical analysis of timing rules for high-speed synchronousVLSI systems

摘要

Timing skew has been the major limitation for high-speednsynchronous operation of a VLSI system. In this paper, a statisticalntiming model that accounts for both static and random timing skew isnproposed. Based on this model, we analyze the timing rules of ansynchronous VLSI system consisting of multiple pipelined stages,nestablish the yield of the system as a function of its devicencharacteristics, and derive the relationship between the maximumnthroughput of such a system and its timing skew. The following timingnschemes are evaluated: conventional pipelining, in which the transmitterncannot initiate the next cycle until the receiver has received the datanand wave pipelining, in which the transmitter initiates the next cyclenas soon as the current data has been sent out. The results show that thenyield of a VLSI system using either of the pipelining schemes exhibitsnthreshold behavior for Gaussian distributed static skew. Furthermore,nthe system throughput is shown to be very sensitive to the random skew