A separated bit-line unified cache: Conciliating small on-chipcache die-area and low miss ratio

摘要

This paper describes an on-chip cache, called a separated bit-linenunified cache, which minimizes the chip-area cost in high-performancenmicroprocessors. This unified cache has two ports; one for theninstruction bus and the other for the data bus. A separated bit-linenmemory hierarchy architecture realizes memory hierarchy design with onlyn10%-20% area overhead. The total cache area can be reduced by more thann20%-30% on the average at capacities of larger than 64 KB with the samenhit rate as the conventional cache. The cache latency reaches 4.2 ns atna supply voltage of 1 V. Additionally, the cache is physicallynaddressable even if the cache has a large capacity