Peephole optimization of asynchronous macromodule networks

摘要

Most high-level synthesis tools for asynchronous circuits takendescriptions in concurrent hardware description languages and generatennetworks of macromodules or handshake components. In this paper, wenpropose a peephole optimizer for these networks. Our peephole optimizernfirst deduces an equivalent blackbox behavior for the network usingnDill's trace-theoretic parallel composition operator. It then applies annew procedure called burst-mode reduction to obtain burst-mode machinesnfrom the deduced behavior. In a significant number of examples, ournoptimizer achieves gate-count improvements by a factor of five, andnspeed (cycle-time) improvements by a factor of two. Burst-mode reductionncan be applied to any macromodule network that is delay insensitive asnwell as deterministic. A significant number of asynchronous circuits,nespecially those generated by asynchronous high-level synthesis tools,nfall into this class, thus making our procedure widely applicable