A layout-based schematic method for very high-speed CMOS celldesign

摘要

In very high-speed CMOS cell design, the result of schematicnsimulation is inaccurate because of missing parasitic components, suchnas diodes and parasitic capacitances. Designer cannot pass enoughninformation to the simulator by conventional transistor symbols,ntherefore, simulation error occurs. In this paper, we address anlayout-based schematic (LBS) method for high-speed CMOS cell design. Innthis method, we introduce several types of MOS transistors and estimatenparasitic wire capacitances by using layout knowledge. The simulationnresults show that the difference between LBS and real layout is muchnsmaller, less than 3% in rise time, compared to in the worst case of upnto 65% in the original schematic. This method can be applied to bothndigital and analog circuits and it is helpful for layout automation.nTime and cost will be reduced in high-speed circuit design