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The spring scheduling coprocessor: a scheduling accelerator

机译:Spring调度协处理器:调度加速器

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The spring scheduling coprocessor is a novel very large scale integration (VLSI) accelerator for multiprocessor real-time systems. The coprocessor can be used for static as well as online scheduling. Many different policies and their combinations can be used (e.g., earliest deadline first, highest value first, or resource-oriented policies such as earliest available time first). In this paper, we describe a coprocessor architecture, a CMOS implementation, an implementation of the host/coprocessor interface and a study of the overall performance improvement. We show that the current VLSI chip speeds up the main portion of the scheduling operation by over three orders of magnitude. We also present an overall system improvement analysis by accounting for the operating system overheads and identify the next set of bottlenecks to improve. The scheduling coprocessor includes several novel VLSI features. It is implemented as a parallel architecture for scheduling that is parameterized for different numbers of tasks, numbers of resources, and internal wordlengths. The architecture was implemented using a single-phase clocking style in several novel ways. The 328 000 transistor custom 2-/spl mu/m VLSI accelerator running with a 100-MHz clock, combined with careful hardware/software co-design results in a considerable performance improvement, thus removing a major bottleneck in real-time systems.
机译:弹簧调度协处理器是一种用于多处理器实时系统的新型超大规模集成(VLSI)加速器。协处理器可用于静态以及在线调度。可以使用许多不同的策略及其组合(例如,最早的截止日期优先,价值最高的优先或资源导向的策略,例如最早的可用时间优先)。在本文中,我们描述了协处理器架构,CMOS实现,主机/协处理器接口的实现以及整体性能改进的研究。我们显示,当前的VLSI芯片将调度操作的主要部分加快了三个数量级。我们还将通过考虑操作系统开销来提出整体系统改进分析,并确定下一组要改进的瓶颈。调度协处理器包括几个新颖的VLSI功能。它实现为用于调度的并行体系结构,该体系结构针对不同数量的任务,资源数量和内部字长进行了参数化。该架构是通过单相时钟方式以几种新颖的方式实现的。运行100 MHz时钟的328 000晶体管定制2- / spl mu / m VLSI加速器,加上精心的硬件/软件协同设计,可显着提高性能,从而消除了实时系统的主要瓶颈。

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