Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm

摘要

The use of a centralised planning in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees. It is particularly well adapted to embedded systems based on low-processing power microcontrollers due to the low overhead it imposes. In this paper a preliminary implementation of a hardware scheduling coprocessor based on the planning paradigm is presented. The Coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU.