Heterogeneous architecture models for interconnect-motivated systemdesign

摘要

On-chip interconnect demand is becoming the dominant factor innmodern processor performance and must be estimated early in the designnprocess. This paper presents a set of heterogeneous architectural modelsnthat combines architecture description and Rent's rule-based wiringnmodels. These architecture models allow flexible heterogeneous systemnspecifications, enabling investigations of prospective designs inndifferent technology scenarios. Comparisons against actual datandemonstrate the models' effectiveness for architecture explorations withnhighly accurate estimations of local and global wiring demand, as wellnas chip area and cycle time. Simulation of two candidate system designsnreveal trends in interconnect delay with increasing architecturalncomplexity, and confirm the need for high computational locality andnshort global wires for future architectures