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A new approach to built-in self-testable datapath synthesis based on integer linear programming

机译:基于整数线性规划的内置自测数据路径综合的新方法

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The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, existing high-level BIST synthesis methods decouple the three tasks and perform the tasks sequentially at the cost of global optimality. They also try to achieve only one objective: minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we propose a new approach to the BIST data path synthesis based on integer linear programming that performs the three register assignment tasks concurrently to yield optimal designs. In addition, our approach finds an optimal register assignment for each k-test session. Therefore, it offers a range of designs with different figures of merit in area and test time. Our experimental results show that our method successfully synthesizes a BIST circuit for every k-test session for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.
机译:高层内置自测(BIST)合成的重点是寄存器分配,其中涉及系统寄存器分配,BIST寄存器分配和互连分配。为了降低分配过程中涉及的复杂性,现有的高级BIST综合方法将三个任务解耦,并以全局最优为代价依次执行任务。他们还尝试仅实现一个目标:最大程度地减少区域开销或测试时间。因此,这些方法无法提供对大设计空间的探索,而这可能会导致局部最优。在本文中,我们提出了一种基于整数线性规划的BIST数据路径综合的新方法,该方法同时执行三个寄存器分配任务以产生最佳设计。此外,我们的方法为每个k测试会话都找到了最佳的寄存器分配。因此,它提供了一系列在面积和测试时间方面具有不同品质因数的设计。我们的实验结果表明,我们的方法成功地为所有六个实验电路的每个k测试会话合成了一个BIST电路。与现有的高级BIST合成方法生成的电路相比,所有BIST电路的面积开销都更好。

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