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A new approach to built-in self-testable datapath synthesis basedon integer linear programming

机译:基于整数线性规划的内置自测数据路径综合新方法

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The focus of high-level built-in self-test (BIST) synthesis isnregister assignment, which involves system register assignment, BISTnregister assignment, and interconnection assignment. To reduce thencomplexity involved in the assignment process, existing high-level BISTnsynthesis methods decouple the three tasks and perform the tasksnsequentially at the cost of global optimality. They also try to achievenonly one objective: minimizing either area overhead or test time. Hence,nthose methods do not render exploration of large design space, which maynresult in a local optimum. In this paper, we propose a new approach tonthe BIST data path synthesis based on integer linear programming thatnperforms the three register assignment tasks concurrently to yieldnoptimal designs. In addition, our approach finds an optimal registernassignment for each k-test session. Therefore, it offers a range ofndesigns with different figures of merit in area and test time. Ournexperimental results show that our method successfully synthesizes anBIST circuit for every k-test session for all six circuits experimented.nAll the BIST circuits are better in area overhead than those generatednby existing high-level BIST synthesis methods
机译:高层内置自测(BIST)综合的重点是寄存器分配,它涉及系统寄存器分配,BISTnregister分配和互连分配。为了减少分配过程中的复杂性,现有的高级BISTns合成方法将三个任务解耦,并以全局最优性为代价依次执行任务。他们还试图实现一个目标:最大限度地减少区域开销或测试时间。因此,没有一种方法不会探索大的设计空间,而这可能导致局部最优。在本文中,我们提出了一种基于整数线性规划的BIST数据路径综合的新方法,该方法同时执行三个寄存器分配任务以产生最佳设计。此外,我们的方法为每个k测试会话都找到了最佳的注册分配。因此,它提供了一系列在面积和测试时间上具有不同品质因数的设计。我们的实验结果表明,我们的方法成功地对所有六个实验电路的每个k测试会话合成了一个BIST电路.n所有BIST电路的面积开销都比现有的高级BIST合成方法所产生的更好

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