Design of VHDL-based totally self-checking finite-state machine anddata-path descriptions

摘要

This paper presents a complete methodology to design a totallynself-checking (TSC) sequential system based on the generic architecturenof finite-state machine and data path (FSMD), such as the one derivingnfrom VHDL specifications. The control part of the system is designed tonbe self-checking by adopting a state assignment providing a constantnHamming distance between each pair of binary codes. The design of thendata path is based on both classical methodologies (e.g., parity, Bergerncode) and ad hoc strategies (e.g., multiplexer cycle) suited for thenspecific circuit structure. Self-checking properties and costs arenevaluated on a set of benchmark FSM's and on a number of VHDL circuits