基于VHDL的MTM总线主模块有限状态机设计

摘要

To describe the State transition of the core unit of MTMobus briefly and rigorously, while reducing the power consumption of FPGA chip, improve the stability of the system, the finite state machine with ＂single process＂ type by VHDL language on the basic of analyzing MTM-bus architecture and finite state machine model of the main module are designed, at the same time,using the circumstance of Quartus/l to implement the compilation of Language code and the timing simulation, functional simulation ; the correctness and effectiveness of this finite state machine design is proved by the analysis of simulation waveforms.%为了能够更简洁严谨地描述MTM总线的主模块有限状态机的状态转换，同时减少FPGA芯片功耗，提高系统稳定性．文中在分析MTM总线结构和主模块有限状态机模型的基础上，基于VHDL语言采用“单进程”式对该有限状态机进行了设计。并在Quartus II开发软件中实现了对语言代码的编译及程序的时序仿真和功能仿真；通过对仿真波形图的分析验证了该状态机设计的正确性和有效性。