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Buffer block planning for interconnect planning and prediction

机译:用于互连规划和预测的缓冲区规划

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This paper studies buffer block planning (BBP) for interconnectnplanning and prediction in deep submicron designs. We first introducenthe concept of a feasible region for buffer insertion, and derive itsnclosed-form formula. We observe that the feasible region for a buffer isnquite large in general even under fairly tight delay constraint.nTherefore, it gives a lot of flexibility to plan for buffer locations.nWe then develop an effective BBP algorithm to perform buffer clusteringnsuch that design objectives such as overall chip area and the number ofnbuffer blocks can be minimized. Effective BBP can plan and predictnsystem-level interconnect by construction, so that accurate interconnectninformation can be used in early design stages to ensure design closure
机译:本文研究用于深亚微米设计中互连规划和预测的缓冲块规划(BBP)。我们首先介绍了一个可行的缓冲区插入区域的概念,并推导了其封闭形式的公式。我们注意到即使在相当严格的延迟约束下,缓冲区的可行区域通常也不大.n因此,它为缓冲区位置的规划提供了很大的灵活性.n然后我们开发了一种有效的BBP算法来执行缓冲区聚类,从而实现了诸如整体芯片面积和nbuffer块的数量可以最小化。有效的BBP可以通过构造来计划和预测系统级互连,因此可以在设计的早期阶段使用准确的互连信息以确保设计封闭

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