Dual-threshold voltage assignment with transistor sizing for lowpower CMOS circuits

摘要

We demonstrate a novel algorithm for assigning the thresholdnvoltage to the gates in a digital random logic complementarynmetal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltagenprocess. The tradeoff between static and dynamic power consumption hasnbeen explored. When used along with device sizing and supply voltagenreduction techniques for low power, the proposed algorithm can reducenthe total power dissipation of a circuit by as much as 50%