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Solving satisfiability problems using reconfigurable computing

机译:使用可重构计算解决可满足性问题

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This paper reports on an innovative approach for solvingnsatisfiability problems for propositional formulas in conjunctive normalnform (SAT) by creating a logic circuit that is specialized to solve eachnproblem instance on field programmable gate arrays (FPGAs). Thisnapproach has become feasible due to recent advances in reconfigurablencomputing and has opened up an exciting new research field in algorithmndesign. SAT is an important subclass of constraint satisfactionnproblems, which can formalize a wide range of application problems. Wenhave developed a series of algorithms that are suitable for a logicncircuit implementation, including an algorithm whose performance isnequivalent to the Davis-Putnam procedure with powerful dynamic variablenordering. Simulation results show that this method can solve a hardnrandom 3-SAT problem with 400 variables within 1.6 min at a clock ratenof 10 MHz. Faster speeds can be obtained by increasing the clock rate.nFurthermore, we have actually implemented a 128-variable 256-clausenproblem instance on FPGAs
机译:本文介绍了一种创新方法,该方法通过创建专用于解决现场可编程门阵列(FPGA)上每个问题实例的逻辑电路来解决合取范式(SAT)中命题公式的可满足性问题。由于可重构n计算的最新进展,这种方法已变得可行,并为算法设计开辟了令人兴奋的新研究领域。 SAT是约束满足问题的重要子类,它可以形式化各种应用问题。 Wenhave开发了一系列适用于逻辑电路实现的算法,包括性能与具有强大动态变量排序功能的Davis-Putnam过程相当的算法。仿真结果表明,该方法可以在10min的时钟频率下,在1.6分钟内解决400个变量的强随机3-SAT问题。通过增加时钟速率可以获得更快的速度。n此外,我们实际上在FPGA上实现了128变量256子句问题实例

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