Analysis of dual-VT SRAM cells with full-swingsingle-ended bit line sensing for on-chip cache

摘要

This paper compares different high-VT and dual-VTn design choices for a large on-chip cache with single-endednsensing in a 0.13 Μm technology generation. The analysis shows thatnthe best design is the one using a dual-VT cell, with minimumnchannel length pass transistors, and low-VT peripheralncircuits. This dual-VT circuit provides 20% performance gainnwith only 1.3× larger active leakage power, and 2.4% larger cellnarea compared to the best design using high-VT cells withnnonminimum channel length pass transistors