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High-speed VLSI architecture for parallel Reed-Solomon decoder

机译:并行Reed-Solomon解码器的高速VLSI架构

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This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. A parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.
机译:本文提出了使用改进的欧几里得算法的高速并行Reed-Solomon(RS)(255,239)解码器体系结构,用于高速每秒数千兆位的光纤系统。流水线化和并行化允许以很高的光纤速率接收输入,并以最小的延迟以相应的高速率发送输出。并行处理体系结构可导致高达10 Gb或更多的速度提升,因为最大可达到的时钟频率通常受修改的Euclidean算法块的关键路径限制。并行RS解码器是通过0.13 / spl mu / m CMOS标准单元技术设计和实现的,电源电压为1.1V。建议使用并行RS解码器,它可以跟上光学传输速率,即可以实现10 Gb / s或更高的速度。拟议中的频道= 4并行RS解码器以770 MHz的时钟频率运行,数据处理速率为26.6 Gb / s。

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