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Switch-factor based loop RLC modeling for efficient timing analysis

机译:基于开关因子的环路RLC建模,可进行有效的时序分析

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Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on the theory of distributed RLC lines and a switch-factor, which is the voltage ratio between two nets. This switch-factor is also known as the Miller factor, and is widely used to model capacitive coupling. The proposed modeling technique can be directly applied to partial RLC netlists extracted using existing parasitic extraction tools without advance knowledge of the return path. The new model captures the impact of neighboring switching activity as it significantly affects the current return path. As demonstrated in our experiments, the new model accurately predicts both upper and lower delay bounds as a function of neighboring switching patterns. Therefore, this approach can be easily implemented into existing timing analysis flows such as max-timing and min-timing analysis. Finally, we apply the new modeling approach to a range of activities across the design process including timing optimization, static timing analysis, high frequency clock design, and data-bus wire planning.
机译:由电感和电容耦合引起的时序不确定性是时序分析中的主要瓶颈之一。在本文中,我们提出了一种有效的环路RLC建模技术,可以通过电感耦合和电容耦合有效地解耦线路。我们基于分布式RLC线路和开关因子(即两个网络之间的电压比)的理论来概括RLC去耦问题。该开关因数也称为米勒因数,被广泛用于建模电容耦合。所提出的建模技术可以直接应用于使用现有寄生提取工具提取的部分RLC网表,而无需事先了解返回路径。新模型捕获了相邻开关活动的影响,因为它显着影响当前的返回路径。如我们的实验所示,新模型可以根据相邻开关模式准确地预测上下延迟界限。因此,这种方法可以很容易地实现到现有的时序分析流程中,例如最大时序和最小时序分析。最后,我们将新的建模方法应用于整个设计过程中的一系列活动,包括时序优化,静态时序分析,高频时钟设计和数据总线布线规划。

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