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Code compression for embedded VLIW processors using variable-to-fixed coding

机译:使用可变到固定编码的嵌入式VLIW处理器的代码压缩

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摘要

In embedded system design, memory is one of the most restricted resources, posing serious constraints on program size. Code compression has been used as a solution to reduce the code size for embedded systems. Lossless data compression techniques are used to compress instructions, which are then decompressed on-the-fly during execution. Previous work used fixed-to-variable coding algorithms that translate fixed-length bit sequences into variable-length bit sequences. In this paper, we present a class of code compression techniques called variable-to-fixed code compression (V2FCC), which uses variable-to-fixed coding schemes based on either Tunstall coding or arithmetic coding. Though the techniques are suitable for both reduced instruction set computer (RISC) and very long instruction word (VLIW) architectures, they favor VLIW architectures which require a high-bandwidth instruction prefetch mechanism to supply multiple operations per cycle, and fast decompression is critical to overcome the communication bottleneck between memory and CPU. Experimental results for a VLIW embedded processor TMS320C6x show that the compression ratios using memoryless V2FCC and Markov V2FCC are around 82.5% and 70%, respectively. Decompression unit designs for memoryless V2FCC and Markov V2FCC are implemented in TSMC 0.25-/spl mu/m technology.
机译:在嵌入式系统设计中,内存是最受限制的资源之一,对程序大小构成了严重限制。代码压缩已被用作减少嵌入式系统代码大小的解决方案。无损数据压缩技术用于压缩指令,然后在执行过程中即时对其进行解压缩。先前的工作使用了固定到可变的编码算法,该算法将固定长度的位序列转换为可变长度的位序列。在本文中,我们提出了一类称为可变固定码压缩(V2FCC)的代码压缩技术,该技术使用基于Tunstall编码或算术编码的可变固定码编码方案。尽管该技术适用于精简指令集计算机(RISC)和超长指令字(VLIW)架构,但它们偏爱VLIW架构,因为VLIW架构需要高带宽指令预取机制才能在每个周期内提供多个操作,因此快速解压对于克服内存和CPU之间的通信瓶颈。 VLIW嵌入式处理器TMS320C6x的实验结果表明,使用无内存V2FCC和Markov V2FCC的压缩率分别约为82.5%和70%。用于无记忆V2FCC和Markov V2FCC的减压单元设计是采用TSMC 0.25- / spl mu / m技术实现的。

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