Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

摘要

Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment lengths and gate scaling are derived. Considerations are presented for integrating LGR into a VLSI design flow in conjunction with related methods. Several logic circuits have been implemented, optimized and verified by LGR. Analytical and simulation results were obtained, showing significant improvement in performance in comparison with traditional repeater insertion, while maintaining low complexity and small area