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Highly-Parallel Decoding Architectures for Convolutional Turbo Codes

机译:卷积Turbo码的高度并行解码架构

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Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and read diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%-34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%
机译:通过提出两种并行解码架构和并行交织器的设计方法,已经研究了用于卷积turbo码的高度并行解码器。为了解决并行解码器中外在信息的存储冲突问题,提出了一种块状方法,其中数据逐行写入,对角线读取,以设计无冲突的并行交织器。此外,针对长turbo码提出了无预热的并行滑动窗口架构,以最大化并行解码器的解码速度。所提出的架构以八并行解码器的存储增加1%的代价将解码速度提高了6%-34%。对于较短的Turbo码(例如512位的长度),提出了一种无预热的并行窗口架构,以将硬件提高12%的代价将速度提高了一倍

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