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Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing

机译:用于信号处理的FHT的功率建模和高效FPGA实现

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Fast Hadamard transform (FHT) belongs to the family of discrete orthogonal transforms and is used widely in image and signal processing applications. In this paper, a parameterizable and scalable architecture for FHT with time and area complexities of $O(2(W+1))$ and $O(2N^{2})$, respectively, has been proposed, where $W$ and $N$ are the word and vector lengths. A novel algorithmic transformation for the FHT based on sparse matrix factorization and distributed arithmetic (DA) principles has been presented. The architecture has been parallelized and pipelined in order to achieve high throughput rates. Efficient and optimized field-programmable gate array implementation of the proposed architecture that yield excellent performance metrics has been analyzed in detail. Additionally, a functional level power analysis and modeling methodology has been proposed to characterize the various power and energy metrics of the cores in terms of system parameters and design variables. The mathematical models that have been derived provide quick presilicon estimate of power and energy measures, allowing intelligent tradeoffs when incorporating the developed cores as subblocks in hardware-based image and video processing systems.
机译:快速哈达玛变换(FHT)属于离散正交变换家族,广泛用于图像和信号处理应用中。在本文中,已经提出了具有时间和区域复杂度分别为$ O(2(W + 1))$和$ O(2N ^ {2})$的FHT的可参数化和可扩展的体系结构,其中$ W $和$ N $是单词和向量的长度。提出了一种基于稀疏矩阵分解和分布式算术(DA)原理的新型FHT算法变换。该架构已经并行化和流水线化,以实现高吞吐率。已经详细分析了所提出的体系结构的高效且优化的现场可编程门阵列实施方案,该实施方案可产生出色的性能指标。另外,已经提出了功能级功率分析和建模方法,以根据系统参数和设计变量来表征核的各种功率和能量度量。所推导的数学模型提供了快速的功率和能量度量的预硅片估算,在将已开发的内核作为基于硬件的图像和视频处理系统中的子模块时,可以进行智能的权衡。

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