An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

摘要

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction ($-$19 dB to the non-SSC situation) and a small core area of 0.25 mm $^{2}$ in 0.13- $mu$m CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm $^{2}$. Moreover, it achieved good jitter tolerance (flat 0.8 UI at $> $1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.