Embedded processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products

Kunio Uchiyama; Fumio Arakawa; Yasuhiko Saito

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Embedded processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products

机译：具有64位架构的嵌入式处理器内核及其针对数字消费品的片上系统集成

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A 64-bit architecture for an embedded pro- cessor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMP/floating-point vector instructions in 32-bit length ISA, And small code size, provided by a conventional 16-bit length ISA.

机译：已经开发出针对下一代数字消费产品的嵌入式处理器的64位体系结构。它具有双模式指令集，并且针对32位长度ISA中的SIMP /浮点矢量指令提供了针对高多媒体性能的优化，而常规的16位长度ISA提供了较小的代码大小。

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来源
《IEICE Transactions on Electronics》 |2001年第2期|p.139-149|共11页
作者
Kunio Uchiyama; Fumio Arakawa; Yasuhiko Saito;
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作者单位

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
embedded processor; RISC; SIMD;

机译：嵌入式处理器风险;信德;
入库时间 2022-08-18 00:36:09

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Embedded processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products

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